Why does the LPM_DIVIDE IP output an incorrect positive remainder during simulation when the numerator is negative? - Why does the LPM_DIVIDE IP output an incorrect positive remainder during simulation when the numerator is negative? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1 and earlier, you might see that the LPM_DIVIDE IP outputs an incorrect positive remainder during simulation when the numerator is negative, even though the LPM_REMAINDERPOSITIVE parameter is set to false. This problem occurs because the LPM_DIVIDE IP does not utilize the LPM_REMAINDERPOSITIVE parameter, resulting in the IP consistently returning a positive remainder in simulation, regardless of the parameter setting. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.2. Custom Fields values: ['novalue'] Troubleshooting 15017638766 False ['LPM_DIVIDE IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 24.1 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']