Why does my simple dual-port memory not function correctly in RTL simulation? - Why does my simple dual-port memory not function correctly in RTL simulation? Description Due to a problem in the Quartus® II software version 11.1 and later, the altsyncram simulation model incorrectly delays the output data by one extra clock cycle when reading from a simple dual-port memory implemented using MLAB resources. This issue occurs when the read-during-write option is set to Old data . Resolution A patch is available to fix this problem in the Quartus II software version 11.1 SP2. Download and install patch 2.32 from the appropriate link below: Download the version 11.1 SP2 patch 2.32 for Windows (.exe) Download the version 11.1 SP2 patch 2.32 for Linux (.tar) Download the Readme for the Quartus II software version 11.1 SP2 patch 2.32 (.txt) This problem is fixed beginning with the Quartus II software version 12.0 SP1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Simulation'] ['FPGA Dev Tools Quartus II Software'] 12.0.1 11.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']