Why is the BUSY bit in the HSSI Command/Status Register not de-asserting in the Ethernet Subsystem IP when invoking SAL Commands? - Why is the BUSY bit in the HSSI Command/Status Register not de-asserting in the Ethernet Subsystem IP when invoking SAL Commands? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the BUSY bit in the HSSI Command/Status Register may be de-asserted in the Ethernet Subsystem IP when invoking Subsystem Abstraction Layer (SAL) Commands. The BUSY bit in the HSSI Command/Status Register determines the status of SAL/NIOS® in the Ethernet Subsystem IP, which helps in posting SAL requests. As the BUSY bit doesn’t go low, all NIOS/SAL involved simulations will hang. This problem happens only in simulation and doesn’t impact hardware behavior. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3.1. Custom Fields values: ['novalue'] Errata 16024692156 False ['Ethernet Subsystem IP (Early Access)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']