Why isn't the chainout adder used by my inferred DSP? - Why isn't the chainout adder used by my inferred DSP? Description Due to a problem in the Quartus® II software version 13.1 and earlier, you may see an adder implemented in registers rather than being absorbed into a DSP block. This occurs when the tool detects a loop going through the DSP block and adder. Resolution To work around this problem, set a keep attribute on the signal looping from the DSP output to it\'s input. This prevents the loop from being detected. Verilog HDL example wire feedback_wire /*synthesis keep*/ VHDL example signal feedback_wire : std_logic; attribute keep: boolean; attribute keep of feedback_wire: signal is true; Custom Fields values: ['novalue'] Troubleshooting novalue False ['DSP'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']