Why do I see abnormal rxdatavalid signal toggling on R-tile Avalon® Streaming FPGA IP for PCI Express* on PIPE direct mode during power state change? - Why do I see abnormal rxdatavalid signal toggling on R-tile Avalon® Streaming FPGA IP for PCI Express* on PIPE direct mode during power state change? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and earlier, you may see abnormal rxdatavalid signal toggling in R-Tile Avalon® Streaming FPGA IP in PIPE direct mode during power stage change. Resolution This problem is fixed in Quartus® Prime Pro Edition Software version 24.1. Custom Fields values: ['novalue'] Troubleshooting 15012624900 False ['R-Tile Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 22.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']