Using Altera® Quartus® Prime Pro Software: Chip Planner - Same Course in Japanese: インテル® Quartus® Prime開発ソフトウェア・プロエディション: Chip Plannerの使用方法 29 Minutes This training will introduce you to the Chip Planner tool that is a part of the Altera® Quartus® Prime Pro software. You will learn how to analyze your design using the Chip Planner features such as chip resource views, critical path analysis and routing congestion analysis. You will learn how to go about floorplanning your design with Logic Logic regions. Finally, you will learn to use the Resource Property Editor to look at fine details of your design. Course Objectives At course completion, you will be able to: perform design analysis with Chip Planner floorplan with logic Lock regions Examine Chip resource implementation details with the resource Property Editor Skills Required Familiarity with Altera® Quartus Prime Pro software and Altera® FPGA devices Familiarity with the concept of floorplanning and location assignments If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OPROCHIPPLAN. FPGA_OPROCHIPPLAN. <p>Using Altera Quartus Prime Pro Software: Chip Planner</p>