Why error is found when generating HDMI RX PHY IP or HDMI TX PHY IP Design Example? - Why error is found when generating HDMI RX PHY IP or HDMI TX PHY IP Design Example? Description Due to the migration of the Nios® II Processor for FPGA to the Nios® V Processor for FPGA, the following error will appear when generating the Design Example from the HDMI RX PHY IP or the HDMI TX PHY IP in the Quartus® Prime Pro Edition Software version 24.1 Resolution There is no workaround for this problem. This problem is fixed beginning with version 25.1.1 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14021914320 False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1.1 24.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']