Why does my Intel® FPGA P-Tile Avalon® memory mapped IP for PCI Express* End Point show lower read performance with the Intel® Quartus® Prime Pro version 19.3? - Why does my Intel® FPGA P-Tile Avalon® memory mapped IP for PCI Express* End Point show lower read performance with the Intel® Quartus® Prime Pro version 19.3? Description The Intel® FPGA P-Tile Avalon® memory mapped IP for PCI Express* supports up to 64 outstanding requests with a Max Read request size of 512 Bytes with the Intel® Quartus® Prime Pro version 19.3. If the round trip latency (Time from Memory Read to Completion) is greater than 1.5 us, the number of outstanding requests may not be enough to saturate the Read throughput. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3. Custom Fields values: ['novalue'] Troubleshooting 14010045894 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express', 'PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 19.3 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['novalue']