Why do I see the read data corruption with the Stratix® 10 FPGA QDRII+ IP when the calibration passes consistently? - Why do I see the read data corruption with the Stratix® 10 FPGA QDRII+ IP when the calibration passes consistently? Description You might observe the read data corruption when there is a large difference in the calibrated DQS-en setting between calibration attempts with the Stratix® 10 FPGA QDRII+ intellectual property (IP). Resolution You can download the patch for Quartus® Prime Software v21.2 release to fix this problem. Please contact Altera support for other Quartus® Prime Software release patches. Readme for the Quartus® Prime Pro Edition Software version 21.2-0.40-readme.txt Patch for the Quartus® Prime Pro Edition Software version 21.2-0.40-windows.exe Patch for the Quartus® Prime Pro Edition Software version 21.2-0.40-linux.run Custom Fields values: ['novalue'] Errata 15010542449 False ['External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.2 21.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']