Why does the R-Tile FPGA IP for Compute Express Link* (CXL*) Type1 Design Example report timing violation with SRNS reference clock mode？ - Why does the R-Tile FPGA IP for Compute Express Link* (CXL*) Type1 Design Example report timing violation with SRNS reference clock mode？ Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3, you might observe timing violations when selecting reference clock mode as SRNS. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 22018717926 False ['R-Tile for Compute Express Link Solution'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.3 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']