You may encounter this error in Stratix® V and Arria® V GZ transceiver devices if you have not connected the outclk_0 port of your Transceiver PLL to the ext_pll_clk input port of the transceiver Native PHY when in external PLL mode. - You may encounter this error in Stratix® V and Arria® V GZ transceiver devices if you have not connected the outclk_0 port of your Transceiver PLL to the ext_pll_clk input port of the transceiver Native PHY when in external PLL mode. Description You may encounter the error below in Stratix® V and Arria® V GZ transceiver devices if you have not connected the outclk_0 port of your Transceiver PLL to the ext_pll_clk input port of the transceiver Native PHY when in external PLL mode. Error: Clock Divider node 'inst|altera_xcvr_native_sv:txcvr_top_inst|sv_xcvr_native:gen_native_inst.xcvr_native_insts[0].gen_bonded_group_native.xcvr_native_inst|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[0].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb' is not properly connected on the 'CLKCDRLOC' port. Custom Fields values: ['novalue'] Troubleshooting novalue False ['PLL'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Arria® V GZ FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']