Error: Verilog HDL Module Instantiation error at bitec_hdmi_tx_aux_encoder.v(0): module "bitec_hdmi_aux_bch" has no parameter named "SYMBOL_PER_CLOCK" - Error: Verilog HDL Module Instantiation error at bitec_hdmi_tx_aux_encoder.v(0): module "bitec_hdmi_aux_bch" has no parameter named "SYMBOL_PER_CLOCK" Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v20.4, you will see this error when integrating the HDMI Intel® FPGA IP 2.0 Tx and the HDMI Intel® FPGA IP 2.1 RX into a design. This is because the module bitec_hdmi_aux_bch has the same module name between the HDMI Intel® FPGA IP 2.0 and the HDMI Intel® FPGA IP 2.1, but the parameters are different. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v21.3. Custom Fields values: ['novalue'] Troubleshooting 1508976425 False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 20.4 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']