Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. - Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. From what i can tell the ADC module only needs a command to select which port to sample so how do i make pin assignments to confirm the ADC in use! Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. hello , sorry , I completed missed that your case here. can you let me know you still facing the same issue , if yes I can attach the design which another customer posted the same in fourm. Thank you , Regards, Sree Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. Hello there , Here attached the screen shot and the modfied design file with ADC block utilization mentioned in the compliation report. As of understood from the design you provided , quartus is optimizing the ADC block since it is no where used in the design. In the modified design i instantiated the ADC input and clock as Input port which restrict the quartus to optimize the same. Hope helps , Thank you , Regards, Sree Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. Hi, I am still facing the same problem. I have been able to check the ADC input if I invoke the Jtag avalon adapter but if I use just the ADC control core the response data is stuck at zero. In the attached project I am trying a simple led blink check using the output of the ADC module. I would really appreciate a prompt reply. Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. Hello , I thought i attached the file to you , Sorry looks i missed out, Can i know you still facing the same issue ? if yes , i will look at again . Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. sorry, i didnt noticed your reply , can i know is that issue resolved ? kindly let me know if you looking for my design files still. Apologize my delay in response. Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. Yes Sree, I am still facing the same issue besides I have attached all files you requested in the past. Can you please provide an solution to the above attached project file as soon as possible? Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. sorry , didnt see your updated post ; Can I know you still facing the issue ? Thank you , Regards, Sree Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. can I know did you get a chance to figure it the issue ? if you still facing the issue kindly let me know ? Thank you, Regards, Sree Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. Hi, Looking forward to your reply! Avdit Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. attached here Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. hmm..Can you attach your project file again (Full project .gar format)? Thank you , Regards, Sree Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. That is not my project at all! Once I open it in quartus the following screenshot shows the different files similar tot the maximator project I mentioned. Can you please ensure the right project files? Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. I dont get you . I modified the project file which you sent to me . Please be clear what you really looking for . All the files related to the project file is already there in attachment. Thanks , Regards, Sree Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. Hi, This is a project created by a blogger 'maximator' which once I edit to my design plans removes the ADC block for some reason. Can you send the project file specific to this query, please? Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. Here is the attachment of qar file .Can you try and let me know ? Thank you , Regards, Sree Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. I added the above suggested logic but to no success. I even tried setting up a new project to double ensure the right part selection from the beginning, however I do not see the ADC module invoked neither the addition of the ADC pins in the final summary. Attached is the screenshot and top level module. I hope this is not a Quartus standard versus lite issue? And if the issue is not software related, can you send me the above depicted correctly compiled project+project files from your end? Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. And if the issue is not software related, can you send me the above depicted correctly compiled project+project files from your end? Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. I hope this is not a Quartus standard versus lite issue? Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. posted a file. Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. I added the above suggested logic but to no success. I even tried setting up a new project to double ensure the right part selection from the beginning, however I do not see the ADC module invoked neither the addition of the ADC pins in the final summary. Attached is the screenshot and top level module. Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. Here is the screen shot of compilation report attached. One thing I noticed that you dont have a RTL for enable the channel or reading the ADC channels , I added a test logic directly enabled the channel "0" , Channel Valid and Channel start. After that I could see in ADC resources in compilation report. I think since the implemented RTL is not using ADC /enable the ADC Quartus is optimization is not instantiating the module. Sorry , I dont know how to attach the file here ,Here is the added logic in the top module for your reference , command_channel <= "00000"; command_valid <= '1'; command_start <= '1'; command_ready <= '1'; process (P_I_CLK100,response_valid) begin if rising_edge(P_I_CLK100) and response_valid = '1' then data_to_display <= response_data; end if; end process; Thank you, Regards, Sree Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. I can confirm the right part number being used- SAU169I7G. If you use the right part number, can i see the flow summary on compilation and if depicts ADC block being used? Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. But the design you send me as per below screen shot , with having error you wont be able to generate the HDL with error in qsys. which one i should be believe your design files or your screen shot ? please clarify Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. If you look at the above screenshot of the flow summary - it clearly shows a SAU device and also shows the no. of ADC blocks in the device but does not show it as used for the design even though the qsys file compiles! Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. Hello , I get chance to look your design , Looks part you selected is not support the ADC features. Only SA and DA parts supports the ADC. Here is the link for device overview for page 5 mentioned in the part number selection. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_overview.pdf when I open the IP in platform designer, i am getting error as mentioned "Error: max_ADC.modular_adc_0: The selected device part number 10M16SCU169I7G does not support ADC" Can you use either SA or DA part to use the ADC feature ? Thank you , Regards, Sree Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. posted a file. Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. I'll try and re phrase the question- How do I assign the ADC1IN1-8 to ports on my top level design? Replies: Re: Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window. I am not following you , Hope you are using Max 10 right ?Can you kindly give more info for the same ? Would it possible to share the design ? Thank you , Regards, Sree - 2019-06-03