Error: (vlog-7) Failed to open design unit file "./../../../rtl/address_decoder/address_decode/altera_avalon_st_handshake_clock_crosser_161/sim/altera_avalon_st_handshake_clock_crosser.v" in read mode. - Error: (vlog-7) Failed to open design unit file "./../../../rtl/address_decoder/address_decode/altera_avalon_st_handshake_clock_crosser_161/sim/altera_avalon_st_handshake_clock_crosser.v" in read mode. Description This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.4. In Windows environment, you may find the following error message during simulation of Low Latency 10G MAC IP example design with Modelsim® when the maximum length of file path is beyond 260 characters Error: (vlog-7) Failed to open design unit file "./../../../rtl/address_decoder/address_decode/altera_avalon_st_handshake_clock_crosser_161/sim/altera_avalon_st_handshake_clock_crosser.v" in read mode. Resolution To avoid the error, reduce the directory depth of simulation files. Custom Fields values: ['novalue'] Troubleshooting 1608664233 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.4 16.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']