How do I connect the RREF_SIPAUX pins on Intel® Stratix® 10 TX devices? - How do I connect the RREF_SIPAUX pins on Intel® Stratix® 10 TX devices? Description The RREF_SIPAUX pins have the same connection guidelines as other RREF pins on Intel® Stratix® 10 devices, and so should be connected to a 2-kΩ resistor (±1%) to GND. Resolution This problem is fixed starting with Intel® Stratix® 10 Device Family Pin Connection Guidelines version 2020.10.23. Custom Fields values: ['novalue'] Troubleshooting 1507414274 False ['novalue'] ['novalue'] novalue novalue ['Stratix® 10 DX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 NX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']