Why does the Avalon-MM DMA Hard IP for PCI Express design stop receiving data? - Why does the Avalon-MM DMA Hard IP for PCI Express design stop receiving data? Description If the RdDmaWaitRequest_i signal is asserted for an extended period of time, the internal storage of the Read DMA Module becomes full, causing the Hard IP for PCI Express® to receive FIFO to become full. Once the FIFO is full, the processing of incoming packets stops for as long as the RdDmaWaitrequest_i signal is asserted. Resolution Redesign your RTL to avoid issuing RdDmaWaitRequest_i. Alternatively, limit its duration to a few clock cycles per transaction. Custom Fields values: ['novalue'] Troubleshooting 1408184259 False ['DMA'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']