Why are FIFO full status bits in 10GBASE-R IP core swapped? - Why are FIFO full status bits in 10GBASE-R IP core swapped? Description In the 10GBASE-R PHY IP core version 10.1 and earlier, the TX_FIFO_FULL and RX_FIFO_FULL status bits are swapped. Affected Configurations This issue affects Stratix® IV and Stratix V implementations of the 10GBASE-R PHY. Solution Status This issue is fixed in the 10GBASE-R PHY IP core version 11.0. Resolution The workaround is to note that for the 10.1 and earlier release RX_FIFO_FULL is actually stored as bit 3 of address 0x82 and TX_FIFO_FULL is stored as bit 4 of address 0x82. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.0 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']