C106 Warnings for Interlaken MegaCore Function 10- and 20-Lane Variations With Transceivers - C106 Warnings for Interlaken MegaCore Function 10- and 20-Lane Variations With Transceivers Description When you compile an Interlaken MegaCore function 10- or 20-lane variation with transceivers, the following warning message appears: Warning: (Medium) Rule C106:Clock signal source should not drive registers triggered by different clock edges. Resolution This issue has no workaround. However, this issue has no design impact. You can ignore this warning message. This issue will be fixed in a future version of the Interlaken MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Interlaken'] ['FPGA Dev Tools Quartus II Software'] novalue 10.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']