How do I implement the half-rate bridge option for connection to a full-rate memory controller? - How do I implement the half-rate bridge option for connection to a full-rate memory controller? Description While using the Quartus® II software versions before 11.0, the half-rate bridge option was a selectable parameter in the memory controller IP megawizard. While using the Quartus® II software versions 11.0 and later, the only Altera IP-supported option for the half-rate bridge is to use the SOPC Builder Avalon-MM DDR Memory Half-Rate Bridge component. This can be used in a QSYS project in the latest release of the Quartus® II software. For documentation on a half-rate bridge, see the Avalon Memory Mapped Bridges chapter of the SOPC Builder User Guide . Resolution While using the Quartus® II software versions 11.0 and later, the only Altera IP-supported option for the half-rate bridge is to use the SOPC Builder Avalon-MM DDR Memory Half-Rate Bridge component. This can be used in a QSYS project in the latest release of the Quartus® II software. Custom Fields values: ['novalue'] Troubleshooting 2205756056 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']