Why do I observe UVM RAL error when simulating the JESD204B or JESD204C Intel® FPGA IP with VCS* MX software version Q-2020.03-SP2? - Why do I observe UVM RAL error when simulating the JESD204B or JESD204C Intel® FPGA IP with VCS* MX software version Q-2020.03-SP2? Description Due to a compatibility problem, you may observe UVM RAL error when simulating the JESD204B or JESD204C Intel® FPGA IP from the Intel® Quartus® Prime Pro Edition Software version 21.1 with VCS* MX software version Q-2020.03-SP2. Resolution This problem has been fixed in Intel® Quartus® Prime Pro Edition Software version 21.3. Custom Fields values: ['novalue'] Troubleshooting 1508996341 False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 21.1 ['Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']