Why do the busy and reconfig_address_en ports go to an unknown state when I simulate dynamic reconfiguration in Stratix II GX devices and newer GX/GT/GZ devices? - Why do the busy and reconfig_address_en ports go to an unknown state when I simulate dynamic reconfiguration in Stratix II GX devices and newer GX/GT/GZ devices? Description ‘busy’ and ‘reconfig_address_en’ ports may show unexpected simulation behavior upon startup in Stratix ® II GX and newer GX/GT/GZ families. Following workaround can be implemented to resolve this simulation issue. Dynamic Reconfiguration Controller block has a reconfig_clk input port. In simulation, if you initialize the reconfig_clk input to a value of 1, then the busy and reconfig_adddress_en ports may go to an unknown state (value of x). This issue occurs in both the VHDL and Verilog models. For example, the following Verilog code would cause this behavior. initial begin reconfig_clk = 1’b1; //clock starts at logic high end always begin #<clock period/2> reconfig_clk = ~reconfig_clk; end To work around this issue, initialize the reconfig_clk input to a value of 0 in the simulation test bench. Related Articles Why is my Busy signal in ALT2GXB_RECONFIG instance stuck at a don't care value in simulation? Custom Fields values: ['novalue'] Troubleshooting novalue False ['Simulation'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'HardCopy™ IV GX ASIC Devices', 'Stratix® II GX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']