Error: Export Address/Command parity error indicator cannot be used if Addr/CMD parity latency is disabled. Addr/CMD parity latency is controlled in the Mode Register Settings section of the Memory tab (advanced setting). - Error: Export Address/Command parity error indicator cannot be used if Addr/CMD parity latency is disabled. Addr/CMD parity latency is controlled in the Mode Register Settings section of the Memory tab (advanced setting). Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.3, you may see this error when you turn on the “Export Address/Command parity error indicator” option in the Intel Agilex® 7 FPGA DDR4 EMIF IP. Resolution Generate the Intel Agilex® 7 FPGA DDR4 EMIF IP without the “Export Address/Command parity error indicator” option turned on. Open the IP file ( .ip ) with a text editor and enable the “AC_PARITY_LATENCY” setting with valid values. Change from: <ipxact:value>DDR4_AC_PARITY_LATENCY_DISABLE<ipxact:value> To: <ipxact:value>DDR4_AC_PARITY_LATENCY_4<ipxact:value> The valid AC_PARITY_LATENCY values are 4, 5, 6, and 8. Refer to the memory vendor datasheet for more details on the address/command parity latency value to apply. Then, regenerate the IP with the option “Export Address/Command parity error indicator” turned on. Additional Information This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.4. Custom Fields values: ['novalue'] Troubleshooting 1508328144 True ['Memory Interfaces and Controllers'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.4 20.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']