JESD204B IP Core Customer Testbench or Design Example Testbench - Simulation Failed for Arria 10 Variants when Using Aldec Riviera Simulator - JESD204B IP Core Customer Testbench or Design Example Testbench - Simulation Failed for Arria 10 Variants when Using Aldec Riviera Simulator Description Simulation for Arria 10 variants will fail if you run simulation with the Riviera simulator. When the simulation completes, the simulation transcript reports the following message: Customer Testbench: “TESTBENCH_FAILED : Unexpected Failure. Probably testbench's issue”. Design Example Testbench: " Pattern Checker(s): No valid data found! JESD204B Tx Core(s): OK! JESD204B Rx Core(s): OK! TESTBENCH_FAILED: SIM FAILED!" The rx_syncstatus signal from the Arria 10 Native PHY will stay at low. This issue is found in Quartus II versions 14.1 and 14.1a10. Resolution There is no workaround. This issue will be fixed in a future release. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']