Warning: Overwriting existing clock: <clock name> - Warning: Overwriting existing clock: <clock name> Description This behavior may been seen in Quartus® II software version 10.0 when your design has either of the following two MegaCore® functions: QDR II and QDR II SRAM Controller with UniPHY v10.0 RLDRAM II Controller with UniPHY v10.0 The warnings occur because all project Synopsys Design Constraint ( .sdc ) files are reread when the Report DDR task is executed in the TimeQuest Timing Analyzer. To work around this problem, modify the <variation_name> _report_timing.tcl with the following steps: Locate the following line: if { ![string match *GUI*DDR* [get_current_timequest_report_folder]] } { Replace the line with the following two lines: set signoff_mode $::quartus(ipc_mode) if { ![string match *GUI*DDR* [get_current_timequest_report_folder]] && !} { This problem is scheduled to be fixed in a future version of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']