Why is the Slot Clock Configuration parameter invisible when the PCIe0/PCIe1 Port Mode parameter is set to Native Endpoint in the GTS AXI Streaming FPGA IP for PCI Express*? - Why is the Slot Clock Configuration parameter invisible when the PCIe0/PCIe1 Port Mode parameter is set to Native Endpoint in the GTS AXI Streaming FPGA IP for PCI Express*? Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, you might notice that the Slot Clock Configuration parameter is invisible when the PCIe0/ PCIe1 Port Mode parameter is set to Native Endpoint. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.1, follow the steps below. 1. To set the parameter to True: i. Open the GTS AXI Streaming FPGA IP for PCI Express and set the Port Mode to Native Endpoint. ii. Go to File and click " Save ". iii. Click " Generate HDL… " and then click on " Done ". 2. To set the parameter to False. i. Open the GTS AXI Streaming FPGA IP for PCI Express* and set the Port Mode to Root Port. ii. Go to P CIe0 -> PCIe0 Settings -> PCIe0 PCI Express / PCI Capabilities -> PCIe0 Link tab to uncheck the Slot Clock Configuration parameter. iii. Go to File and click " Save " . iv. Click " Generate HDL… " and then click on " Done ". v. Open the IP in the IP Parameter Editor in the Quartus® project to set the Port Mode to Native Endpoint. vi. Repeat Step iii and iv. This problem will be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 15018024114 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']