Why rx_pcs_fully_aligned signal keep toggling in the GTS PMA/FEC Direct PHY IP when configured to the PCS Direct mode (IEEE MII Interface)? - Why rx_pcs_fully_aligned signal keep toggling in the GTS PMA/FEC Direct PHY IP when configured to the PCS Direct mode (IEEE MII Interface)? Description The rx_pcs_fully_aligned signal keeps toggling in the GTS PMA/FEC Direct PHY IP when configured to the PCS Direct mode (IEEE MII Interface) due to the one-bit shift in PCS data mapping for 80-bit data. Resolution To work around this problem, follow the table below for data bit mapping if using GTS PMA/FEC Direct PHY IP in PCS Direct mode (IEEE MII Interface). MSB LSB TX Parallel Data RX Parallel Data 75 i_tx_mii_c[7] o_rx_mii_c[7] 74 67 i_tx_mii_d[63:56] o_rx_mii_d[63:56] 66 i_tx_mii_c[6] o_rx_mii_c[6] 65 58 i_tx_mii_d[55:48] o_rx_mii_d[55:48] 57 i_tx_mii_c[5] o_rx_mii_c[5] 56 49 i_tx_mii_d[47:40] o_rx_mii_d[47:40] 48 i_tx_mii_c[4] o_rx_mii_c[4] 47 40 i_tx_mii_d[39:32] o_rx_mii_d[39:32] 38 i_tx_mii_valid o_rx_mii_valid 37 i_tx_mii_am (RSFEC) Reserved(Firecode FEC) o_rx_mii_am (RSFEC) Reserved (Firecode FEC) 35 i_tx_mii_c[3] o_rx_mii_c[3] 34 27 i_tx_mii_d[31:24] o_rx_mii_d[31:24] 26 i_tx_mii_c[2] o_rx_mii_c[2] 25 18 i_tx_mii_d[23:16] o_rx_mii_d[23:16] 17 i_tx_mii_c[1] o_rx_mii_c[1] 16 9 i_tx_mii_d[15:8] o_rx_mii_d[15:8] 8 i_tx_mii_c[0] o_rx_mii_c[0] 7 0 i_tx_mii_d[7:0] o_rx_mii_d[7:0] Also, bit 76, which was captured as o_tx_mii_ready in previous versions of the GTS PMA/FEC Direct PHY IP user guide, is obsolete. It is not recommended to use this bit. This will not impact the functionality. Custom Fields values: ['novalue'] Troubleshooting 16024505035 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software'] 24.3 24.2 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']