Why does my PCIe* Independent GPIO PERST# test design fail to compile when I target the GXF_2ND_PERSTn signal on Pin CN11 of the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023)? - Why does my PCIe* Independent GPIO PERST# test design fail to compile when I target the GXF_2ND_PERSTn signal on Pin CN11 of the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023)? Description Due to a mistake on the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023), the PCIe* Independent GPIO PERST# is shown going to two Pin locations: GXF_2ND_PERSTn signal on Pin CN11 on Sheet 22 should be DNU (Do Not Use). GXF_1V2_2ND_PERSTn signal on Pin B46 on Sheet 16 is a valid GPIO on Bank 3A, and this should be used. Resolution When testing Independent GPIO PERST# in Bifurcated 2x8 Mode on the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023), either test in Single PERST# Mode when both x8 Cores are connected to the same host, or use Pin B46, which is a valid GPIO in Bank 3A. Related IP Cores F-Tile Avalon® Streaming IP for PCI Express* Multi-Channel DMA FPGA IP for PCI Express* Custom Fields values: Troubleshooting 18044028451 ['Interfaces PCIe Multi-Channel DMA (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.3 ['Agilex™ 7 FPGA F-Series'] ['Agilex™ 7 FPGA F-Series 023 Dev Kit']