Why is the byte enable signal disconnected when generating 2-Port RAM IP core for Intel® Stratix® 10 devices? - Why is the byte enable signal disconnected when generating 2-Port RAM IP core for Intel® Stratix® 10 devices? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.2, you may see the byte enable signal is not connected to 2-Port RAM IP core for Intel® Stratix® 10 devices Resolution This problem has been fixed beginning with version 20.3 of the Intel® Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 18011793265 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.3 20.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']