Why does the HPS boot up delay after trigger HPS cold reset via the external reset pin? - Why does the HPS boot up delay after trigger HPS cold reset via the external reset pin? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, when the multi-flash support feature is introduced, the flash recovery flow tries to recover the flash by re-attempting the calibration step before resetting the flash. This recovery approach causes the flash recovery flow to fail, then triggers the watchdog timer. Resolution The fix is to remove the re-calibration step and reset the flash device during the flash recovery flow. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15018562361 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']