Why is avl_ready de-asserting after a read or write request? - Why is avl_ready de-asserting after a read or write request? Description When using the DDR3 UniPHY quarter rate controller, you may notice that avl_ready goes low immediately following a read or write request. This leads to poor read and write efficiency by the controller. There is a known issue with the quarter rate controller where it de-asserts avl_ready following a burst command with a burst size larger than one. The controller de-asserts avl_ready for one cycle stalling the Avalon command queue. Resolution The workaround is to use a burst size of one to achieve maximum efficiency or to use a larger burst size, such as 32 or 64, to minimize the effect of the one cycle stall. This issue will be fixed in a future version of the Quartus® II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']