Stratix V Hard IP for PCI Express Root Port Base Address Register Decode Not Working Correctly - Stratix V Hard IP for PCI Express Root Port Base Address Register Decode Not Working Correctly Description The rx_st_bardec output signal is not working correctly for Root Port variants of the Stratix V Hard IP for PCI Express IP Core. The rx_st_bardec signal fails to assert for first data cycle of MRd , MWr , IOWR and IORD TLPs when the address of the TLP matches the address range of a BAR. Resolution The workaround is to implement the BAR decoding logic for Root Ports in user logic to determine which BAR (BAR0 or BAR1) is a TLP target. You can determine the BAR settings from your Root Port\'s Configuration Software. Alternatively, you can also determine the settings by decoding the Type 0 Configuration Writes that the Root Port sends on Avalon-ST to set up the BAR registers in the Root Port. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']