Is it possible to increase the SEU error FIFO depth when implementing the Advanced SEU Detection Intel® FPGA IP for Intel® Stratix® 10 FPGA in Off-Chip Lookup Sensitivity Processing mode? - Is it possible to increase the SEU error FIFO depth when implementing the Advanced SEU Detection Intel® FPGA IP for Intel® Stratix® 10 FPGA in Off-Chip Lookup Sensitivity Processing mode? Description Yes, when instantiating the Advanced SEU Detection Intel® FPGA IP for Intel® Stratix® 10 FPGA, you can use the Single Event Upset (SEU) error FIFO depth parameter to modify the size of the internal FIFO. Resolution The value on this parameter will take effect in the two implementation modes supported by the IP: On-Chip Lookup Sensitivity Processing and Off-Chip Lookup Sensitivity Processing. Information about this has been added in the Intel® Stratix® 10 SEU Mitigation User Guide starting with version 19.3. Custom Fields values: ['novalue'] Troubleshooting 14010113819 False ['Advanced SEU Detection IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.4 19.3 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']