Power Optimization - 48 Minutes This is part 2 of 2. Designing for low-power in today’s high-speed FPGA designs is more important than ever. Knowing the final design’s power usage early in the design process is necessary for making power supply design and power budgeting decisions. This training will give you the knowledge and tools you need to perform highly accurate estimates of power usage using the Quartus® Prime software. In this second part, now that you know how to perform a power analysis, you’ll see how to use this information to optimize a design to minimize power through the use of power-driven compilation options and through following low power design guidelines. Course Objectives At course completion, you will be able to: Optimize power by performing a power-driven compilation Reduce power usage by following low-power design Guidelines Skills Required Basic understanding of the FPGA design flow and the Quartus Prime software Basic understanding of timing analysis using the TimeQuest timing analyzer Basic knowledge of performing simulations in 3rd-party EDA simulation tools If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ODSWPWR2. FPGA_ODSWPWR2. <p>Power Optimization</p>