Why is there port width mismatch when I try to connect the encoder output directly to the decoder input of the LDPC Intel® FPGA IP core? - Why is there port width mismatch when I try to connect the encoder output directly to the decoder input of the LDPC Intel® FPGA IP core? Description The output of the LDPC Intel® FPGA IP core encoder cannot be connected directly to the input of the LPDC Intel FPGA IP core decoder. The output data of encoder will need to undergo log-likelihood ratio (LLR) and soft bits conversion prior to feeding into input of the decoder. You will need to create the conversion logic using the soft logic. Resolution There is no workaround required. Custom Fields values: ['novalue'] Troubleshooting 1507219116 False ['IP Low-Density Parity-Check (LDPC) IP-LDPC'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.0 ['Arria® II FPGAs', 'Arria® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'MAX® 10 10 FPGAs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']