Verilog HDL Basics - Same Course in Simplified Chinese: Verilog HDL基础 Same Course in Japanese: Verilog HDL 基礎編 47 Minutes This course will provide an overview of the Verilog hardware description language (HDL) and its use in programmable logic design. The emphasis is on the synthesis constructs of Verilog HDL; however, you will also learn about some simulation constructs. You will gain a basic understanding of Verilog HDL that will enable you to begin creating your design using Altera® FPGAs. Course Objectives Understand the origin of the Verilog HDL language Understand the language basics Use Verilog HDL Building blocks (design units) including modules, ports, processes, and assignments Model code styles including behavioral code style and structural code style Understand the design methodologies of Verilog HDL and the differences between simulation Models and Synthesis Models Skills Required Background in digital logic design Prior knowledge of a programming language (e.g., "C" language) is a plus No prior knowledge of Verilog HDL or Altera® Quartus® Prime software is required If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OHDL1120. FPGA_OHDL1120. <p>Verilog HDL Basics</p>