Will the receiver side of a transceiver channel be available during ATX PLL calibration of Stratix V GX/GT and Arria V GZ devices? - Will the receiver side of a transceiver channel be available during ATX PLL calibration of Stratix V GX/GT and Arria V GZ devices? Description During initial ATX PLL calibration immediately after configuration of Stratix® V GX/GT and Arria® V GZ devices, the receiver will not be available. Subsequent ATX PLL calibration processes initiated by the user will not affect the receiver data path. Related Articles ........ATX PLL..RX......... Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GZ FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']