Why does changing the csr_lmfc_offset parameter in the JESD204B Intel® FPGA IP not affect the deterministic latency when the product of F and K is 1024? - Why does changing the csr_lmfc_offset parameter in the JESD204B Intel® FPGA IP not affect the deterministic latency when the product of F and K is 1024? Description Due to a known problem in the Intel® Quartus® Prime Pro software version 21.1 and earlier and the Intel® Quartus® Prime Standard Edition version 20.1 and earlier, when using the JESD204B Intel® FPGA IP in TX mode with Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10 and Intel® Agilex™ devices, if the product of F and K is the maximum value of 1024 , configuring csr_lmfc_offset has no effect in shifting the internal LMFC edge of the IP. The internal LMFC counter defaults to start counting from 0 upon SYSREF detection. Resolution To work around this issue, use the LMFC adjustment or RBD offset in the RX converter device to achieve deterministic latency when FxK=1024 . This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.2. Custom Fields values: ['novalue'] Troubleshooting 1508883863 False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.2 14.0 ['Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']