How can I simulate the ASMI Intel FPGA IP with internal and external memory models when using the Intel® Arria® 10 and Intel Cyclone® 10 GX devices? - How can I simulate the ASMI Intel FPGA IP with internal and external memory models when using the Intel® Arria® 10 and Intel Cyclone® 10 GX devices? Description For internal memory model use case, we currently only support simulation of the ASMI Intel FPGA IP in Intel® Arria® 10 and Intel Cyclone® 10 GX devices with the flash model for the EPCQL1024 serial configuration device. Follow the steps in the Resolution section to perform the simulation with the internal EPCQL model (Note: This simulation was tested with Mentor Graphics* ModelSim* SE simulation software). Resolution Create a simulation model for ASMI block and set the enable_sim parameter to true in file: <project directory>/<ASMIIP name>/<altera_asmi_parallel_<quartus_version>>/<sim>/<ip_name>altera_asmi_parallel_<quartus_version>_<unique_ip_id>.v Create a testbench file with initialization of ASMI block as shown in the following example: <ip_name>_altera_asmi_parallel_<quartus_version>_<unique_ip_id> dut( .clkin (clkin), // clkin.clk .fast_read (fast_read), // fast_read.fast_read .rden (rden), // rden.rden .addr (addr), // addr.addr .read_status (read_status), // read_status.read_status .write (write), // write.write .datain (datain), // datain.datain .sector_protect (sector_protect), // sector_protect.sector_protect .sector_erase (sector_erase), // sector_erase.sector_erase .die_erase (die_erase), // die_erase.die_erase .wren (wren), // wren.wren .read_rdid (read_rdid), // read_rdid.read_rdid .en4b_addr (en4b_addr), // en4b_addr.en4b_addr .ex4b_addr (ex4b_addr), // ex4b_addr.ex4b_addr .reset (reset), // reset.reset .sce (sce), // sce.sce .dataout (dataout), // dataout.dataout .busy (busy), // busy.busy .data_valid (data_valid), // data_valid.data_valid .status_out (status_out), // status_out.status_out .illegal_write (illegal_write), // illegal_write.illegal_write .illegal_erase (illegal_erase), // illegal_erase.illegal_erase .read_address (read_address), // read_address.read_address .rdid_out (rdid_out) // rdid_out.rdid_out ); Run simulation. To simulate with an external memory model, follow these steps: Create a simulation model for ASMI block and set the enable_sim parameter to false in file: <project directory>/<ASMI IP name>/<altera_asmi_parallel_<quartus_version>>/<sim>/<ip_name>altera_asmi_parallel_<quartus_version>_<unique_ip_id>.v Create a testbench file with initialization of ASMI block (as shown in the previous code example): Create a wrapper for external memory In a simulation project, compile the following files for your working folder: flash simulation model asmi_sim_model design wrapper testbench file(s) Run simulation. Custom Fields values: ['novalue'] Troubleshooting 1807084650 False ['Generic Component'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']