Error (272006): Port addressstall_a is connected in the ALTDPRAM megafunction -- MLAB block for device family Stratix V of the ALTDPRAM megafunction cannot use wraddrstall signal - Error (272006): Port addressstall_a is connected in the ALTDPRAM megafunction -- MLAB block for device family Stratix V of the ALTDPRAM megafunction cannot use wraddrstall signal Description The Quartus® II software might generate this error when compiling a design that targets a Stratix® V device. This problem might occur if your design contains a memory megafunction generated with the parameter editor in the Quartus II software versions 12.0 SP1 and earlier. The error occurs if the memory has the wr_addressstall port connected and is implemented using MLAB resources. Resolution To work around this problem, either change the memory type to M20K or disable the wr_addressstall port in the parameter editor. This problem is fixed starting with the Quartus® II software version 14.0 where the wr_addressstall port can be used with Stratix V MLAB memory blocks but only when the Read-During-Write option is set to Old memory contents appear . Custom Fields values: ['novalue'] Troubleshooting 2205815020 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.0 11.0 ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']