Integrating Memory Interfaces IP in Altera® FPGA Devices - Same Course in Japanese: Generation 10デバイスにおけるメモリ・インタフェースIPの統合 Same Course in Simplified Chinese: 第10代器件集成的内存接口IP 62 Minutes This training is part 2 of 4. Altera® Stratix® 10, Arria® 10, and Cyclone® 10 devices introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 2.666 Gbps on some devices. This part of the training discusses how to use the IP Parameter Editor in the Quartus® Prime Pro edition software or Platform Designer to create and parameterize the altera_emif IP for a standard FPGA or an SoC variant. It also shows how to constrain the IP in a device using either the Pin Planner or Interface Planner, found only in the Altera Quartus Prime Pro Edition software. Finally, resource sharing is presented to demonstrate how easy it is to implement multiple interfaces in a single device with minimal resource usage. Course Objectives At course completion, you will be able to: Parameterize the new altera_emif IP for the latest Altera® FPGA devices Constrain the IP to specific device resources Share device resources to implement multiple interfaces in a single device Skills Required Background in digital logic design Basic knowledge of memory interfaces Familiarity with the Quartus Prime software Familiarity with memory interfaces in Altera FPGA devices from the listed prerequisite training classes If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OMEM1122. FPGA_OMEM1122. <p>Integrating Memory Interfaces IP in Altera FPGA Devices</p>