FND-05 - Quartus® Prime Design Software: Fundamentals - 2 Days - Enroll Now This course provides engineers with a practical introduction to the Altera® FPGA primary development environment, Quartus Prime. Participants learn to navigate the Quartus Prime interface, manage FPGA projects from creation to programming, configure target devices, apply timing and pin constraints, and understand the complete FPGA design flow within the tool. The course emphasizes efficient project setup, best practices for tool usage, and a deep understanding of the compilation pipeline — from RTL entry through synthesis, placement and routing, timing analysis, and device configuration. Special attention is given to timing closure using the Timing Analyzer and to in-system debugging with the SignalTap Logic Analyzer. Course Content: 1. Introduction to Altera FPGAs and the Quartus® Prime Toolchain 2. Quartus Prime Interface Overview: Menus, Windows, and Toolbars 3. Creating and Configuring a New Quartus Prime Project 4. Device Selection and Target Family Overview 5. Design Entry Methods: Schematic, VHDL, Verilog, and SystemVerilog 6. Compiling a Design: Analysis & Synthesis, Fitter, Assembler, Timing Analysis 7. Understanding Compilation Reports and Messages 8. Pin Assignment and the Assignment Editor 9. Location and I/O Standard Constraints 10. The Pin Planner: Visual Pin Assignment 11. Timing Constraints Fundamentals: Clock Definitions and I/O Delays 12. Functional and Timing Simulation with ModelSim/Questa 13. Introduction to the Quartus IP Catalog and Parameterised Modules 14. Instantiating and Configuring IP Cores (PLL, FIFO, RAM) 15. Timing Analysis Fundamentals: Setup, Hold, Recovery, Removal 16. Timing Analyzer: GUI and Tcl Interface 17. Writing SDC Constraints: create_clock, create_generated_clock, set_input_delay, set_output_delay 18. Timing Reports: Paths, Slack, and Critical Path Analysis 19. Timing Exceptions: false_path, multicycle_path, set_max_delay 20. Compilation Strategies and Optimization Settings 21. Using the Chip Planner and Logic Lock Regions 22. In-System Debugging with SignalTap Logic Analyzer 23. Configuring SignalTap: Triggers, Sampling Depth, and Clock Domain 24. In-System Memory Content Editor and In-System Sources and Probes 25. Power Estimation and the PowerPlay Power Analyzer 26. I/O Termination Strategies and I/O Timing Optimization 27. Introduction to Platform Designer for System Level Design 28. HPS Integration for Cyclone® V / Arria® SoC Devices 29. FPGA Configuration Methods: JTAG, AS, PS, and Remote Update 30 Quartus Programmer: SRAM, Flash, and Configuration Devices 31. Tcl Scripting in Quartus Prime: Automation and Batch Compilation 32. Incremental Compilation and Design Partitioning 33. Engineering Change Orders (ECO) with the ECO Compile Flow 34. Revision Management and Project Archiving 35. Design Methodology Best Practices and Q&A / Review Prerequisites: - Basic understanding of digital logic design (combinational and sequential circuits) - Familiarity with at least one HDL: VHDL, Verilog, or SystemVerilog (ability to read and understand RTL code) - Experience with a Windows 11 or Linux desktop environment - Understanding of general FPGA concepts: LUTs, flip flops, I/O banks, and clocking resources Recommended (not mandatory): - Basic familiarity with simulation concepts and testbenches - Understanding of synchronous design methodology and clock domain crossing principles - Basic command line/terminal usage for running scripts Tools Required: - Quartus Prime Pro Edition - ModelSim - Altera FPGA Edition - Questa Altera FPGA Edition - Nios® V Processor Embedded Design Suite - ModelSim PE Student Edition - Python - Visual Studio Code Course Code: FND-05. FA_QUARTUS.