Simulating FiFo IP using Quartus Pro 23.3 - Simulating FiFo IP using Quartus Pro 23.3 Hello, I am attempting to simulate the Fifo IP using the Questa Starter Edition. I am targeting the Stratix 10 GX. It is imperative that I use Quartus Pro and Questa SE to perform these simulations. Here are the steps I am taking, Steps Im taking: Quartus Prime Pro 23.3, Questa Free Standard New Project Wizard Dir: D:/Work/QuestaSims/SingleClk24to24Fifo Name: Fifo Top: FifoTop Stratix 10 GX No added files Select “Questa Intel FPGA edition” for simulation Open Fifo IP editor Everything Default Generate HDL (VHDL) Selected Model Sim for simulator script Generate TestBench Selected VHDL Close Parameter editor Add tb qsys to project files Click "Generate Simulator Setup scripts" under tools Its at this point that I am unable to make any more progress. I have followed the Questa tutorials provided by Siemans, in the tutorial documents found within the questa install directory. However, these don't account for the added files generated by the IP. I am wondering what steps I need to take after these, so that I have all the needed files to begin simulation? I have referenced these documents Introduction to Intel® FPGA IP Cores Intel® Stratix® 10 Embedded Memory User Guide Advanced Platform Designer (Part 1): Simulation Replies: Re: Simulating FiFo IP using Quartus Pro 23.3 Hi, There is any solution? Replies: Re: Simulating FiFo IP using Quartus Pro 23.3 I believe I have provided the solution. With that, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Thank you and have a great day! Best Regards, Richard Tan Replies: Re: Simulating FiFo IP using Quartus Pro 23.3 Hi, Are you able to resolve the issue? Regards, Richard tan Replies: Re: Simulating FiFo IP using Quartus Pro 23.3 I attached an example simulation with the DCFIFO IP. This is run with different testbench and with the IP standalone only (without the fifo_top.v). I also add usedw signal in it. You may refer this as a guidelines. Best Regards, Richard Tan Replies: Re: Simulating FiFo IP using Quartus Pro 23.3 Hi Richard, Thanks for the response, it has helped me move along this problem. After clicking “Generate Simulator Setup Script.” Open Questa Change the directory to the mentor directory in my project files Then “do mentor_example.do” ( this is a simulator file I wrote, taken from the link provided) This opens the Questa Simulator viewer where I can see the objects and attempt to run the sim However, I am still unable to successfully simulate the FiFo. It seems that Questa doesn’t seem to be communicating with the IP. What I mean is that I can see my test bench stimulus coming through on the waveform viewer but it doesn’t seem to have any effect on the FiFo IP. I have tried running the simulation for different time intervals so that I wasn’t missing anything but no matter what the FiFo doesn’t output any data. It never sends the Empty flag low, or the Full flag high. Even after I wait many CC after sending it data, and overflowing it. I am attaching my project files in a Zip. The relevant ones are mentor_example.do, fifo_top.v, and FiFoTestBench.v Thanks for the support! Max McCune Replies: Re: Simulating FiFo IP using Quartus Pro 23.3 Dropping a note to ask if my last reply was helpful to you? Do you need any further assistance from my side? Best Regards, Richard Tan Replies: Re: Simulating FiFo IP using Quartus Pro 23.3 The next step in the simulation flow, after you have generated the simulation setup script in Quartus, is to write a simulation script. This is a user guide for the standard simulation flow (without the Qsys). Kindly refer to section [1.5] on how to create the simulation script and then to section [1.6] 'Compile and Simulate the Design' at the following link: Link: https://www.intel.com/content/www/us/en/docs/programmable/691278/21-3/create-the-simulation-script.html I have also attached a simple zip file (altera_avalon_bfm_master.zip) for a BFM simulation, but this does not include the FIFO IP. It's just to give you a hands-on understanding of how things work. At some points, you can check out this example design with FIFO IP and FIFO2 (this design does not use the qsys system). Link: https://www.intel.com/content/www/us/en/design-example/714682/intel-stratix-10-fpga-fifo-vs-fifo2-simulation-design-example.html Best Regards, Richard Tan