Why is there a failure in the design if we are doing design migration for Agilex™ 3/Agilex™ 5 FPGA, with GTS Reset Sequencer from version 25.3 to 25.3.1? - Why is there a failure in the design if we are doing design migration for Agilex™ 3/Agilex™ 5 FPGA, with GTS Reset Sequencer from version 25.3 to 25.3.1? Description Following an IP upgrade from version 25.3 to version 25.3.1 of the Quartus® Prime Pro Edition software, there is a port renaming involved for Agilex™ 3 FPGAS or Agilex™ 5 FPGA GTS Reset Sequencer IP. There are two ports that has been renamed for improvement purpose. Resolution For a workaround, you need to update the existing port name to the new ports that are available in the GTS Reset Sequencer IP. The existing ports that will require update are: i_src_rs_refclk_status_bus_out (25.3) --> i_src_rs_refclk_status_bus (25.3.1) o_src_rs_refclk_status_bus_in (25.3) --> o_src_rs_refclk_status_bus (25.3.1) Custom Fields values: ['novalue'] Troubleshooting 16028743538 novalue ['Transceivers & Basic Functions'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3 ['Agilex™ 3 FPGAs and SoCs', 'Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']