Why does my eSRAM Intel Agilex® 7 FPGA IP not meet the maximum performance specification? - Why does my eSRAM Intel Agilex® 7 FPGA IP not meet the maximum performance specification? Description Due to a problem in the Intel Quartus® Prime Pro Edition Software version 19.3 and later, the eSRAM Intel Agilex® 7 FPGA IP may not meet the maximum performance specification due to a hold violation. Resolution To work around this problem, modify the design file by adding “ (* altera_attribute = "-name HYPER_REGISTER_DELAY_CHAIN 100"*) ” to the eSRAM IP instance. For Example: (* altera_attribute = "-name HYPER_REGISTER_DELAY_CHAIN 100"*) esram esram_inst( .esram0_ram_input_clk (clk_500), ...... This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.2. Custom Fields values: ['novalue'] Troubleshooting 14013827667 1509061184 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.2 20.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']