Why does my Signal Tap Logic Analyzer get stuck on "Waiting for Clock"? - Why does my Signal Tap Logic Analyzer get stuck on "Waiting for Clock"? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3, you might see the data acquisition gets stuck in the “Waiting for clock” state, and all connections to the instance are listed as “unconnected” in the compilation report. This problem occurs when the Signal Tap Logic Analyzer instance has uppercase characters in its name. Resolution To work around this problem, rename the Signal Tap instance using only lowercase characters and recompile the project. Custom Fields values: ['novalue'] Troubleshooting 18033908320 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.4 23.3 ['Programmable Logic Devices'] ['Signal Tap'] ['novalue'] ['novalue']