Why is the O-RAN FPGA IP reset polarity is inverted in platform designer? - Why is the O-RAN FPGA IP reset polarity is inverted in platform designer? Description Due to a problem in the O-RAN FPGA IP version 1.9.1 and earlier, the input reset signal maps to incorrect polarity when instantiated in Platform Designer. As the input reset to the O-RAN FPGA IP is active low, Platform Designer should automatically map the signal type to reset_n instead of type reset . Resolution To work around this problem, perform the following steps : 1). Open the oran_hw.tcl file available at <quartus_instalation_dir>/ip/altera_cloud/oran/src/. 2). Find and replace the following lines of code: a). From add_interface_port rst_tx_n rst_tx_n reset INPUT 1 To add_interface_port rst_tx_n rst_tx_n reset_n INPUT 1. b). From add_interface_port rst_rx_n rst_rx_n reset INPUT 1 To add_interface_port rst_rx_n rst_rx_n reset_n INPUT 1 c). From add_interface_port rst_csr_n rst_csr_n reset INPUT 1 To add_interface_port rst_csr_n rst_csr_n reset_n INPUT 1 Custom Fields values: ['novalue'] Troubleshooting 16021578521 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 22.3 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 DX FPGA', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 NX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']