How do I reduce the simulation time required to simulate F-Tile Transceiver-based designs that use FEC? - How do I reduce the simulation time required to simulate F-Tile Transceiver-based designs that use FEC? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, the C-models required for fast simulation times of F-Tile transceiver-based designs that use FEC are not enabled by default. Resolution To work around this problem, perform the following steps, depending on which simulator you are using: VCS Open the simulation setup script ( vcs_setup.sh ) in the Synopsys VCS simulation directory Append the following option to USER_DEFINED_SIM_OPTIONS USER_DEFINED_SIM_OPTIONS ="-sv_lib $QUARTUS_INSTALL_DIR/eda/sim_lib/libdb_gdr_fec" Append the following option to USER_DEFINED_ELAB_OPTIONS USER_DEFINED_ELAB_OPTIONS=”+define+gdrb_GDR_FEC_FASTSIM” Xcelium Open the simulation setup script ( xcelium_setup.sh ) in the Xcelium simulation directory. Append the following option to USER_DEFINED_SIM_OPTIONS USER_DEFINED_SIM_OPTIONS ="-sv_lib $QUARTUS_INSTALL_DIR/eda/sim_lib/libdb_gdr_fec" Append the following option to USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_COMPILE_OPTIONS=”+define+gdrb_GDR_FEC_FASTSIM” Questasim Open the simulation setup script ( msim_setup.tcl ) in the Mentor simulation directory. Append the following option to USER_DEFINED_ELAB_OPTIONS USER_DEFINED_ELAB_OPTIONS ="-sv_lib $QUARTUS_INSTALL_DIR/eda/sim_lib/libdb_gdr_fec" Append the following option to USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_COMPILE_OPTIONS=”+define+gdrb_GDR_FEC_FASTSIM” Riviera Riviera simulator is currently not supported. This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3. Custom Fields values: ['novalue'] Troubleshooting 15015937349 False ['F-Tile PMA/FEC Direct PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']