Arria 10 PCI Express User Guides Show Incorrect Timing for the Transaction Layer Configuration Space Signals - Arria 10 PCI Express User Guides Show Incorrect Timing for the Transaction Layer Configuration Space Signals Description The Arria 10 Avalon-ST Interface for PCIe Solutions User Guide and Arria 10 Avalon-MM Interface for PCIe Solutions User Guide show an incorrect timing diagram for Transaction Layer Configuration Space Signals (tl_cfg*) . The Transaction Layer Configuration Space Interface is a multi-cycle path. You must sample this interface in the middle of the 8-cycle window to ensure proper operation. Resolution This problem is corrected in the October 31, 2016 versions of these user guides. Custom Fields values: ['novalue'] Troubleshooting novalue True ['PCI Express'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25