Error: (vsim-3058) The width (1) of Verilog port 'scaninb' does not match the array length (8) of its VHDL connection - Error: (vsim-3058) The width (1) of Verilog port 'scaninb' does not match the array length (8) of its VHDL connection Description You may see this error if you generate Altera® Multiply Adder in Quartus® II v13.0. Resolution This issue has been fixed in Quartus II software version 14.0 and later. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.0 13.0 ['Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']