Introduction to Hyper-Pipelining - 23 Minutes Hyper-Pipelining is the second of three steps to improving your design’s performance when targeting the Hyperflex® architecture found in Altera® FPGAs, with each step allowing you to move you up the performance curve. In this training, you will learn the meaning of Hyper-Pipelining, how it differs from conventional pipelining and how to implement Hyper-Pipelining in your design with the help of the Quartus® Prime Pro software’s Fast Forward analysis tool. Course Objectives At course completion, you will be able to: Improve your Hyperflex architecture design performance by implementing zero-latency Hyper-pipelining Skills Required Familiarity with FPGA/CPLD design flow Familiarity with the Quartus Prime Pro design software Familiarity with Verilog or VHDL synthesizable design structures Familiarity with the Hyperflex architecture If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OS10HYPPIPE. FPGA_OS10HYPPIPE. <p>Introduction to Hyper-Pipelining</p>